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The z10 is a microprocessor chip made by IBM for their System z10 mainframe computers, released February 26, 2008.〔(IBM System z: The Future Runs on the IBM System z10 Enterprise Class )〕 It was called "z6" during development.〔(【引用サイトリンク】 url=http://speleotrove.com/decimal/IBM-z6-mainframe-microprocessor-Webb.pdf )〕 == Description == The processor implements the CISC z/Architecture and has four cores. Each core has a 64 KB L1 instruction cache, a 128 KB L1 data cache and a 3 MB L2 cache (called the L1.5 cache by IBM). Finally, there is a 24 MB shared L3 cache (referred to as the L2 cache by IBM). The chip measures 21.7×20.0 mm and consists of 993 million transistors fabricated in IBM's 65 nm SOI fabrication process (CMOS 11S), supporting speeds of 4.4 GHz and above – more than twice the clock speed as former mainframes – with a 15 FO4 cycle. Each z10 chip has two 48 GB/s (48 billion bytes per second) SMP hub ports, four 13 GB/s memory ports, two 17 GB/s I/O ports, and 8765 contacts. The z10 processor was co-developed with and shares many design traits with the POWER6 processor, such as fabrication technology, logic design, execution unit, floating-point units, bus technology (GX bus) and pipeline design style, i.e., a high frequency, low latency, deep (14 stages in the z10), in-order pipeline. However, the processors are quite dissimilar in other respects, such as cache hierarchy and coherency, SMP topology and protocol, and chip organization. The different ISAs result in very different cores – there are 894 unique z10 instructions, 75% of which are implemented entirely in hardware. The z/Architecture is a CISC architecture, backwards compatible to the IBM System/360 architecture from the 1960s. Additions to the z/Architecture from the previous z9 EC processor include: * 50+ new instructions for improved code efficiency * software/hardware cache optimizations * support for 1 MB page frames * decimal floating point fully implemented in hardware. Error detection and recovery is emphasized, with error-correcting code (ECC) on L2 and L3 caches and buffers, and extensive parity checking elsewhere; in all over 20,000 error checkers on the chip. Processor state is buffered in a way that allows precise core retry for almost all hardware errors. 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「IBM z10」の詳細全文を読む スポンサード リンク
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